SH7721 datasheet(748/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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748 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 686 of 1458

REJ09B0033-0300

21.3.2

Control Register (SICTR)

SICTR is a 16-bit readable/writable register that sets the SIOF operating state.

Bit

Bit Name

Initial

Value

R/W

Description

SCKE

R/W

Serial Clock Output Enable

This bit is valid in master mode.

0: Disables the SIOFSCK output (outputs 0)

1: Enables the SIOFSCK output

• If this bit is set to 1, the SIOF initializes the baud

rate generator and initiates the operation. At the

same time, the SIOF outputs the clock generated by

the baud rate generator to the SIOFSCK pin.

This bit is initialized in module stop mode.

FSE

R/W

Frame Synchronous Signal Output Enable

This bit is valid in master mode.

0: Disables the SIOFSYNC output (outputs 0)

1: Enables the SIOFSYNC output

• If this bit is set to 1, the SIOF initializes the frame

counter and initiates the operation.

This bit is initialized in module stop mode.

13 to 10



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SH7721 Datasheet(PDF) 748 Page - Renesas Technology Corp