SH7721 datasheet(751/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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751 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 689 of 1458

REJ09B0033-0300

21.3.3

Transmit Data Register (SITDR)

SITDR is a 32-bit write-only register that specifies the SIOF transmit data.

SITDR is initialized by the conditions specified in section 37, List of Registers, or by a transmit

reset caused by the TXRST bit in SICTR.

SITDR is initialized in module stop mode.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 16

SITDL

15 to 0

All 0

Left-Channel Transmit Data

Specify data to be output from the SIOFTxD pin as left-

channel data. The position of the left-channel data in

the transmit frame is specified by the TDLA bit in

SITDAR.

• These bits are valid only when the TDLE bit in

SITDAR is set to 1.

15 to 0

SITDR

15 to 0

All 0

Right-Channel Transmit Data

Specify data to be output from the SIOFTxD pin as

right-channel data. The position of the right-channel

data in the transmit frame is specified by the TDRA bit

in SITDAR.

• These bits are valid only when the TDRE bit and

TLREP bit in SITDAR are set to 1 and cleared to 0,

respectively.

SH7721 Datasheet(PDF) 751 Page - Renesas Technology Corp