SH7721 datasheet(755/1524 Pages) RENESAS

755 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 693 of 1458

REJ09B0033-0300

21.3.7

Status Register (SISTR)

SISTR is a 16-bit read-only register that shows the SIOF state. Each bit in this register becomes an

SIOF interrupt source when the corresponding bit in SIIER is set to 1.

SISTR is initialized in module stop mode.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

TCRDY

Transmit Control Data Ready

0: Indicates that a write to SITCR is disabled

1: Indicates that a write to SITCR is enabled

• If SITCR is written when this bit is cleared to 0, SITCR

is over-written and the previous contents of SITCR

are not output from the SIOFTxD pin.

• This bit is valid when the TXE bit in SITCR is set to 1.

• This bit indicates a state of the SIOF. If SITCR is

written, the SIOF clears this bit.

• If the issue of interrupts by this bit is enabled, an

SIOF interrupt is issued.

TFEMP

Transmit FIFO Empty

0: Indicates that transmit FIFO is not empty

1: Indicates that transmit FIFO is empty

• This bit is valid when the TXE bit in SICTR is 1.

• This bit indicates a state; if SITDR is written, the SIOF

clears this bit.

• If the issue of interrupts by this bit is enabled, an

SIOF interrupt is issued.

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