SH7721 datasheet(757/1524 Pages) RENESAS

757 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 695 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

RFFUL

Receive FIFO Full

0: Receive FIFO not full

1: Receive FIFO full

• This bit is valid when the RXE bit in SICTR is 1.

• This bit indicates a state; if SIRDR is read, the SIOF

clears this bit.

• If the issue of interrupts by this bit is enabled, an

SIOF interrupt is issued.

RDREQ

Receive Data Transfer Request

0: Indicates that the size of valid space in the receive

FIFO does not exceed the size specified by the RFWM

bit in SIFCTR.

1: Indicates that the size of valid space in the receive

FIFO exceeds the size specified by the RFWM bit in

SIFCTR.

A receive data transfer request is issued when the valid

space in the receive FIFO exceeds the size specified by

the RFWM bit in SIFCTR.

When using receive data transfer through the DMAC, this

bit is always cleared by one DMAC access. After DMAC

access, when conditions for setting this bit are satisfied,

the SIOF again indicates 1 for this bit.

• This bit is valid when the RXE bit in SICTR is 1.

• This bit indicates a state; if the size of valid space in

the receive FIFO is less than the size specified by the

RFWM bit in SIFCTR, the SIOF clears this bit.

• If the issue of interrupts by this bit is enabled, an

SIOF interrupt is issued.

7, 6



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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