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SH7721 Datasheet(PDF) 760 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 760 Page - Renesas Technology Corp |
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760 / 1524 page  Section 21 Serial I/O with FIFO (SIOF) Rev. 3.00 Jan. 18, 2008 Page 698 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 1 RFUDF 0 R/W Receive FIFO Underflow 0: No receive FIFO underflow 1: Receive FIFO underflow A receive FIFO underflow means that reading of SIRDR has occurred when the receive FIFO is empty. When a receive FIFO underflow occurs, the value of data read from SIRDR is not guaranteed. • This bit is valid when the RXE bit in SICTR is 1. • When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. • If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 0 RFOVF 0 R/W Receive FIFO Overflow 0: No receive FIFO overflow 1: Receive FIFO overflow A receive FIFO overflow means that writing has occurred when the receive FIFO is full. When a receive FIFO overflow occurs, the SIOF indicates overflow, and receive data is lost. • This bit is valid when the RXE bit in SICTR is 1. • When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. • If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. |
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