SH7721 datasheet(763/1524 Pages) RENESAS

763 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 701 of 1458

REJ09B0033-0300

21.3.9

FIFO Control Register (SIFCTR)

SIFCTR is a 16-bit readable/writable register that indicates the area available for the

transmit/receive FIFO transfer.

Bit

Bit Name

Initial

Value

R/W

Description

TFWM2

TFWM1

TFWM0

R/W

Transmit FIFO Watermark

000: Issue a transfer request when 16 stages of the

transmit FIFO are empty.

001: Setting prohibited

010: Setting prohibited

011: Setting prohibited

100: Issue a transfer request when 12 or more stages of

the transmit FIFO are empty.

101: Issue a transfer request when 8 or more stages of

the transmit FIFO are empty.

110: Issue a transfer request when 4 or more stages of

the transmit FIFO are empty.

111: Issue a transfer request when 1 or more stages of

transmit FIFO are empty.

• A transfer request to the transmit FIFO is issued by

the TDREQ bit in SISTR.

• The transmit FIFO is always used as 16 stages of the

FIFO regardless of these bit settings.

TFUA4

TFUA3

TFUA2

TFUA1

TFUA0

Transmit FIFO Usable Area

Indicate the number of words that can be transferred by

the CPU or DMAC as B'00000 (full) to B'10000 (empty).

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