SH7721 datasheet(765/1524 Pages) RENESAS

765 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 703 of 1458

REJ09B0033-0300

21.3.10

Clock Select Register (SISCR)

SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the

master clock. SISCR can be specified when the TRMD1 and TRMD0 bits in SIMDR are specified

as B'10 or B'11.

Bit

Bit Name

Initial

Value

R/W

Description

MSSEL

R/W

Master Clock Source Selection

0: Uses the input signal of the SIOFMCLK pin as the

master clock

1: Uses P

φ as the master clock

The master clock is the clock input to the baud rate

generator.

MSIMM

R/W

Master Clock Direct Selection

0: Uses the output clock of the baud rate generator as the

serial clock

1: Uses the master clock itself as the serial clock



Reserved

This bit is always read as 0. The write value should

always be 0.

BRPS4

BRPS3

BRPS2

BRPS1

BRPS0

R/W

Prescalar Setting

Set the master clock division ratio according to the count

value of the prescalar of the baud rate generator.

The range of settings is from B'00000 (

× 1/1) to B'11111

(

× 1/32).

7 to 3



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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