SH7721 datasheet(764/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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764 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 702 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

RFWM2

RFWM1

RFWM0

R/W

Receive FIFO Watermark

000: Issue a transfer request when 1 stage or more of the

receive FIFO are valid.

001: Setting prohibited

010: Setting prohibited

011: Setting prohibited

100: Issue a transfer request when 4 or more stages of

the receive FIFO are valid.

101: Issue a transfer request when 8 or more stages of

the receive FIFO are valid.

110: Issue a transfer request when 12 or more stages of

the receive FIFO are valid.

111: Issue a transfer request when 16 stages of the

receive FIFO are valid.

• A transfer request to the receive FIFO is issued by the

RDREQ bit in SISTR.

• The receive FIFO is always used as 16 stages of the

FIFO regardless of these bit settings.

RFUA4

RFUA3

RFUA2

RFUA1

RFUA0

Receive FIFO Usable Area

Indicate the number of words that can be transferred by

the CPU or DMAC as B'00000 (empty) to B'10000 (full).

SH7721 Datasheet(PDF) 764 Page - Renesas Technology Corp