SH7721 datasheet(766/1524 Pages) RENESAS

766 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 704 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

BRDV2

BRDV1

BRDV0

R/W

Baud rate generator's Division Ratio Setting

Set the frequency division ratio for the output stage of the

baud rate generator.

000: Prescalar output

× 1/2

001: Prescalar output

× 1/4

010: Prescalar output

× 1/8

011: Prescalar output

× 1/16

100: Prescalar output

× 1/32

101: Setting prohibited

110: Setting prohibited

111: Prescalar output

× 1/1*

The final frequency division ratio of the baud rate

generator is determined by BRPS

× BRDV (maximum

1/1024).

Note: *This setting is valid only when the BRPS4 to

BRPS0 bits are set to B'00000.

21.3.11

Transmit Data Assign Register (SITDAR)

SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a

frame (slot number).

Bit

Bit Name

Initial

Value

R/W

Description

TDLE

R/W

Transmit Left-Channel Data Enable

0: Disables left-channel data transmission

1: Enables left-channel data transmission

14 to 12



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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