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SH7721 Datasheet(PDF) 767 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 767 Page - Renesas Technology Corp

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Section 21
Serial I/O with FIFO (SIOF)
Rev. 3.00 Jan. 18, 2008 Page 705 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial
Value
R/W
Description
11
10
9
8
TDLA3
TDLA2
TDLA1
TDLA0
0
0
0
0
R/W
R/W
R/W
R/W
Transmit Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a transmit
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Transmit data for the left channel is specified in the
SITDL bit in SITDR.
7
TDRE
0
R/W
Transmit Right-Channel Data Enable
0: Disables right-channel data transmission
1: Enables right-channel data transmission
6
TLREP
0
R/W
Transmit Left-Channel Repeat
0: Transmits data specified in the SITDR bit in SITDR
as right-channel data
1: Repeatedly transmits data specified in the SITDL bit
in SITDR as right-channel data
• This bit setting is valid when the TDRE bit is set to
1.
• When this bit is set to 1, the SITDR settings are
ignored.
5, 4
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3
2
1
0
TDRA3
TDRA2
TDRA1
TDRA0
0
0
0
0
R/W
R/W
R/W
R/W
Transmit Right-Channel Data Assigns 3 to 0
Specify the position of right-channel data in a transmit
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Transmit data for the right channel is specified in
the SITDR bit in SITDR.



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