SH7721 datasheet(769/1524 Pages) RENESAS

769 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 707 of 1458

REJ09B0033-0300

21.3.13

Control Data Assign Register (SICDAR)

SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a

frame (slot number). SICDAR can be specified only when the FL bit in SIMDR is specified as

1xxx (x: Don't care.).

Bit

Bit Name

Initial

Value

R/W

Description

CD0E

R/W

Control Channel 0 Data Enable

0: Disables transmission and reception of control

channel 0 data

1: Enables transmission and reception of control

channel 0 data

14 to 12



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CD0A3

CD0A2

CD0A1

CD0A0

R/W

Control Channel 0 Data Assigns 3 to 0

Specify the position of control channel 0 data in a

receive or transmit frame as B'0000 (0) to B'1110 (14).

1111: Setting prohibited

• Transmit data for the control channel 0 data is

specified in the SITD0 bit in SITCR.

• Receive data for the control channel 0 data is stored

in the SIRD0 bit in SIRCR.

CD1E

R/W

Control Channel 1 Data Enable

0: Disables transmission and reception of control

channel 1 data

1: Enables transmission and reception of control

channel 1 data

6 to 4



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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