SH7721 datasheet(768/1524 Pages) RENESAS

768 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 706 of 1458

REJ09B0033-0300

21.3.12

Receive Data Assign Register (SIRDAR)

SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a

frame (slot number).

Bit

Bit Name

Initial

Value

R/W

Description

RDLE

R/W

Receive Left-Channel Data Enable

0: Disables left-channel data reception

1: Enables left-channel data reception

14 to 12



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

RDLA3

RDLA2

RDLA1

RDLA0

R/W

Receive Left-Channel Data Assigns 3 to 0

Specify the position of left-channel data in a receive

frame as B'0000 (0) to B'1110 (14).

1111: Setting prohibited

• Receive data for the left channel is stored in the

SIRDL bit in SIRDR.

RDRE

R/W

Receive Right-Channel Data Enable

0: Disables right-channel data reception

1: Enables right-channel data reception

6 to 4



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

RDRA3

RDRA2

RDRA1

RDRA0

R/W

Receive Right-Channel Data Assigns 3 to 0

Specify the position of right-channel data in a receive

frame as B'0000 (0) to B'1110 (14).

1111: Setting prohibited

• Receive data for the right channel is stored in the

SIRDR bit in SIRDR.

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