SH7721 datasheet(762/1524 Pages) RENESAS

762 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 700 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

RFFULE

R/W

Receive FIFO Full Enable

0: Disables interrupts due to receive FIFO full

1: Enables interrupts due to receive FIFO full

RDREQE

R/W

Receive Data Transfer Request Enable

0: Disables interrupts due to receive data transfer

requests

1: Enables interrupts due to receive data transfer

requests

7, 6



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SAERRE

R/W

Slot Assign Error Enable

0: Disables interrupts due to slot assign error

1: Enables interrupts due to slot assign error

FSERRE

R/W

Frame Synchronization Error Enable

0: Disables interrupts due to frame synchronization error

1: Enables interrupts due to frame synchronization error

TFOVFE

R/W

Transmit FIFO Overflow Enable

0: Disables interrupts due to transmit FIFO overflow

1: Enables interrupts due to transmit FIFO overflow

TFUDFE

R/W

Transmit FIFO Underflow Enable

0: Disables interrupts due to transmit FIFO underflow

1: Enables interrupts due to transmit FIFO underflow

RFUDFE

R/W

Receive FIFO Underflow Enable

0: Disables interrupts due to receive FIFO underflow

1: Enables interrupts due to receive FIFO underflow

RFOVFE

R/W

Receive FIFO Overflow Enable

0: Disables interrupts due to receive FIFO overflow

1: Enables interrupts due to receive FIFO overflow

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