SH7721 datasheet(761/1524 Pages) RENESAS

761 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 699 of 1458

REJ09B0033-0300

21.3.8

Interrupt Enable Register (SIIER)

SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each

bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an

interrupt.

Bit

Bit Name

Initial

Value

R/W

Description

TDMAE

R/W

Transmit Data DMA Transfer Request Enable

Transmits an interrupt as an interrupt to the CPU/DMA

transfer request. The TDREQE bit can be set as transmit

interrupts.

0: Used as a CPU interrupt

1: Used as a DMA transfer request to the DMAC

TCRDYE

R/W

Transmit Control Data Ready Enable

0: Disables interrupts due to transmit control data ready

1: Enables interrupts due to transmit control data ready

TFEMPE

R/W

Transmit FIFO Empty Enable

0: Disables interrupts due to transmit FIFO empty

1: Enables interrupts due to transmit FIFO empty

TDREQE

R/W

Transmit Data Transfer Request Enable

0: Disables interrupts due to transmit data transfer

requests

1: Enables interrupts due to transmit data transfer

requests

RDMAE

R/W

Receive Data DMA Transfer Request Enable

Transmits an interrupt as an interrupt to the CPU/DMA

transfer request. The RDREQE bit can be set as receive

interrupts.

0: Used as a CPU interrupt

1: Used as a DMA transfer request to the DMAC

RCRDYE

R/W

Receive Control Data Ready Enable

0: Disables interrupts due to receive control data ready

1: Enables interrupts due to receive control data ready

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