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SH7721 Datasheet(PDF) 753 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 753 Page - Renesas Technology Corp

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Section 21
Serial I/O with FIFO (SIOF)
Rev. 3.00 Jan. 18, 2008 Page 691 of 1458
REJ09B0033-0300
21.3.5
Transmit Control Data Register (SITCR)
SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF.
SITCR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: Don't care.).
SITCR is initialized in module stop mode.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 16
SITC0
15 to 0
All 0
R/W
Control Channel 0 Transmit Data
Specify data to be output from the SIOFTxD pin as
control channel 0 transmit data. The position of the
control channel 0 data in the transmit or receive frame
is specified by the CD0A bit in SICDAR.
• These bits are valid only when the CD0E bit in
SICDAR is set to 1.
15 to 0
SITC1
15 to 0
All 0
R/W
Control Channel 1 Transmit Data
Specify data to be output from the SIOFTxD pin as
control channel 1 transmit data. The position of the
control channel 1 data in the transmit or receive frame
is specified by the CD1A bit in SICDAR.
• These bits are valid only when the CD1E bit in
SICDAR is set to 1.



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