SH7721 datasheet(749/1524 Pages) RENESAS

749 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 687 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

TXE

R/W

Transmit Enable

0: Disables data transmission from the SIOFTxD pin

1: Enables data transmission from the SIOFTxD pin

• This bit setting becomes valid at the start of the next

frame (at the rising edge of the SIOFSYNC signal).

• When the 1 setting for this bit becomes valid, the

SIOF issues a transmit transfer request according to

the setting of the TFWM bit in SIFCTR. When

transmit data is stored in the transmit FIFO,

transmission of data from the SIOFTxD pin begins.

• This bit is initialized upon a transmit reset.

This bit is initialized in module stop mode.

RXE

R/W

Receive Enable

0: Disables data reception from SIOFRxD

1: Enables data reception from SIOFRxD

• This bit setting becomes valid at the start of the next

frame (at the rising edge of the SIOFSYNC signal).

• When the 1 setting for this bit becomes valid, the

SIOF begins the reception of data from the

SIOFRxD pin. When receive data is stored in the

receive FIFO, the SIOF issues a reception transfer

request according to the setting of the RFWM bit in

SIFCTR.

• This bit is initialized upon receive reset.

This bit is initialized in module stop mode.

7 to 2



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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