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SH7721 Datasheet(PDF) 747 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 747 Page - Renesas Technology Corp

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Section 21
Serial I/O with FIFO (SIOF)
Rev. 3.00 Jan. 18, 2008 Page 685 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial
Value
R/W
Description
4
SYNCDL
0
R/W
Data Pin Bit Delay for SIOFSYNC Pin
Valid when the SIOFSYNC signal is output as
synchronous pulse. Only one-bit delay is valid for
transmission in slave mode.
0: No bit delay
1: 1-bit delay
3 to 0
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Table 21.2
Operation in Each Transfer Mode
Transfer Mode
Master/Slave
SIOFSYNC
Bit Delay
Control Data Method*
1
Slave mode 1
Slave
Synchronous
pulse
Slot position
Slave mode 2
Slave
Synchronous
pulse
Secondary FS
Master mode 1
Master
Synchronous
pulse
SYNCDL bit
Slot position
Master mode 2
Master
L/R
No*
2
Not supported
Notes: *1 The control data method is valid only when the FL bit is specified as 1xxx. (x: Don't
care.)
*2 Depending on the timing to start SYNC signal output in master mode 2, the SYNC
signal of the head frame in the high period can be extended to I bit. For details, see
section 21.5, Usage Notes.



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