SH7721 datasheet(745/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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745 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 683 of 1458

REJ09B0033-0300

21.3.1

Mode Register (SIMDR)

SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.

Bit

Bit Name

Initial

Value

R/W

Description

TRMD1

TRMD0

R/W

Transfer Mode 1, 0

Select transfer mode. For details, see table 21.2.

00: Slave mode 1

01: Slave mode 2

10: Master mode 1

11: Master mode 2

SYNCAT

R/W

SIOFSYNC Pin Valid Timing

Indicates the position of the SIOFSYNC signal to be

output as a synchronization pulse.

0: At the start-bit data of frame

1: At the last-bit data of slot

REDG

R/W

Receive Data Sampling Edge

0: The SIOFRxD signal is sampled at the falling edge of

SIOFSCK (The SIOFTxD signal is transmitted at the

rising edge of SIOFSCK.)

1: The SIOFRxD signal is sampled at the rising edge of

SIOFSCK (The SIOFTxD signal is transmitted at the

falling edge of SIOFSCK.)

Note: This bit is valid only in master mode.

SH7721 Datasheet(PDF) 745 Page - Renesas Technology Corp