SH7721 datasheet(736/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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736 / 1524 page

Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 674 of 1458

REJ09B0033-0300

Yes

RDRF=1 ?

Yes

RDRF=1 ?

Last receive

- 1?

Slave receive mode

Clear AAS in ICSR

Clear ACKBT in ICIER to 0

Dummy-read ICDRR

Read RDRF in ICSR

Read ICDRR

Set ACKBT in ICIER to 1

Read ICDRR

Read RDRF in ICSR

Read ICDRR

End

Yes

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[1] Clear the AAS flag.*

[2] Set acknowledge to the transmit device.

[3] Dummy-read ICDRR.

[4] Wait for 1 byte to be received.

[5] Check whether it is the (last receive - 1).

[6] Read the receive data.

[7] Set acknowledge of the last byte.

[8] Read the (last byte - 1) of receive data.

[9] Wait the last byte to be received.

[10] Read for the last byte of receive data.

Note: When one byte is received, steps [2] to [6] are skipped; step [7]

is executed after step [1]. Setp [8] is ICDRR dummy read.

Figure 20.17

Sample Flowchart for Slave Receive Mode

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