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SH7721 Datasheet(PDF) 732 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 732 Page - Renesas Technology Corp |
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732 / 1524 page  Section 20 I 2C Bus Interface (IIC) Rev. 3.00 Jan. 18, 2008 Page 670 of 1458 REJ09B0033-0300 20.4.6 Noise Canceller The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 20.16 shows a block diagram of the noise canceller circuit. The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the peripheral clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. C Q D March detector Internal SCL or SDA signal SCL or SDA input signal Sampling clock Sampling clock Peripheral clock period Latch Latch C Q D Figure 20.13 Block Diagram of Noise Conceller 20.4.7 Example of Use Flowcharts in respective modes that use the I 2C bus interface are shown in figures 20.17 to 20.20. |
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