SH7721 datasheet(787/1524 Pages) RENESAS

787 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 725 of 1458

REJ09B0033-0300

(5)

Transmit/Receive Reset

The SIOF can separately reset the transmit and receive units by setting the following bits to 1.

• Transmit reset: TXRST bit in SICTR

• Receive reset: RXRST bit in SICTR

Table 21.11 shows the details of initialization upon transmit or receive reset.

Table 21.11 Transmit and Receive Reset

Type

Objects Initialized

Transmit reset

SITDR

Transmit FIFO write pointer and read pointer

TCRDY, TFEMP, and TDREQ bits in SISTR

TXE bit in SICTR

Receive reset

SIRDR

Receive FIFO write pointer and read pointer

RCRDY, RFFUL, and RDREQ bits in SISTR

RXE bit in SICTR

Notes: Refer to the following procedure to operate the transmit reset/receive reset.

Set the master clock source in the peripheral clock. (Write 1 (master clock = P

(peripheral clock)) to the MSSEL bit in the SISCR register).

Set the prescaler count value of the baud rate generator to 1/1. (Write "00000" (division

ratio = 1/1) to BRPS bits 4 to 0 in the SISCR register).

Set the division ratio in the bit rate generator's output level to 1/1. (Write "111" (division

ratio =1/1) to BRDV bits 2 to 0 in the SISCR register).

Reset transmit/receive operation. (To reset, write "1" to the TXRST or RXRST bit in the

SICTR register).

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