SH7721 datasheet(784/1524 Pages) RENESAS

784 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 722 of 1458

REJ09B0033-0300

(2)

Reception in Master Mode

Figure 21.10 shows an example of settings and operation for master mode reception.

Flow Chart

SIOF Settings

SIOF Operation

Start

Set SIMDR, SISCR, SITDAR,

SIRDAR, SICDAR, and SIFCTR

Set operating mode, serial clock,

slot positions for transmit/receive

data, slot position for control data,

and FIFO request threshold value

Set the SCKE bit in SICTR to 1

Start SIOFSCK output

Set the FSE and RXE bits

in SICTR to 1

Clear the RXE bit in SICTR to 0

RDREQ = 1?

Yes

Read SIRDR

Store SIOFRXD receive data in SIRDR

synchronously with SIOFSYNC

Transfer ended?

Set operation start for

baud rate generator

Set the start for frame

synchronous signal output and

enable reception

Read receive data

Set to disable reception

Output serial clock

Output frame

synchronous signal

Reception

End reception

No.

Issue receive transfer

request according to the

receive FIFO threshold

value

End

Set the FSE bit in SICTR to 0

Set the MSSEL bit in SISCR to 1

Set BRDV=111

and BPRS=00000 in SISCR

Start the setting FSE=0,

TXE=0 and other bit.

Add pulse (0

→1→0)

to the RXRST in SISCR

Reset the master clock source

and baud rate in SISCR

Synchronize this LSI internal

frame with FSE=0 if restarting

recept later.

Execute internal initialization

of the bit rate generator

if restarting recept later.

'No' requires further setting

if transmission is not restarted

(No).

When returning to the same

recept mode from here,

go back to No.4, FSE setting,

on this flowchart.

Go to "Start" on each flowchart.

Yes

Change other

transmit mode?

Figure 21.10

Example of Receive Operation in Master Mode

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