SH7721 datasheet(782/1524 Pages) RENESAS

782 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 720 of 1458

REJ09B0033-0300

Table 21.10 Conditions to Issue Receive Request

RFWM2 to RFWM0

Number of

Requested Stages

Receive Request

Used Areas

000

Valid data is 1 stage or more

100

Valid data is 4 stages or more

101

Valid data is 8 stages or more

110

Valid data is 12 stages or more

Smallest

111

Valid data is 16 stages

Largest

The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the

FIFO size (the number of FIFOs). Accordingly, an overflow error or underflow error occurs if data

area or empty area exceeds sixteen FIFO stages. The FIFO transmit or receive request is canceled

when the above condition is not satisfied even if the FIFO is not empty or full.

(3)

Number of FIFOs

The number of FIFO stages used in transmission and reception is indicated by the following

• Transmit FIFO: The number of empty FIFO stages is indicated by the TFUA4 to TFUA0 bits

in SIFCTR.

• Receive FIFO: The number of valid data stages is indicated by the RFUA4 to RFUA0 bits in

SIFCTR.

The above indicate possible data numbers that can be transferred by the CPU or DMAC.

SH7721 Datasheet(PDF) 782 Page - Renesas Technology Corp