SH7721 datasheet(778/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 716 of 1458

REJ09B0033-0300

Table 21.6

Audio Mode Specification for Transmit Data

Bit

Mode

TDLE

TDRE

TLREP

Monaural

Stereo

Left and right same audio output

Note:

x: Don't care

Table 21.7

Audio Mode Specification for Receive Data

Bit

Mode

RDLE

RDRE

Monaural

Stereo

Note:

Left and right same audio mode is not supported in receive data.

To execute 8-bit monaural transmission or reception, use the left channel.

(2)

Control Data

Control data is written to or read from by the following registers.

• Transmit control data write: SITCR (32-bit access)

• Receive control data read: SIRCR (32-bit access)

Figure 21.6 shows the control data and bit alignment in SITCR and SIRCR.

24 23

16 15

8 7

24 23

16 15

8 7

(a) Control data: One channel

(b) Control data: Two channels

Control data

(channel 0)

Control data

(channel 0)

Control data

(channel 1)

Figure 21.6

Control Data Bit Alignment

SH7721 Datasheet(PDF) 778 Page - Renesas Technology Corp

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