SH7721 datasheet(781/1524 Pages) RENESAS

781 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 719 of 1458

REJ09B0033-0300

21.4.6

FIFO

(1)

Overview

The transmit and receive FIFOs of the SIOF have the following features.

• 16-stage 32-bit FIFOs for transmission and reception

• The FIFO pointer can be updated in one read or write cycle regardless of access size of the

CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)

(2)

Transfer Request

The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt

sources.

• FIFO transmit request: TDREQ (transmit interrupt source)

• FIFO receive request: RDREQ (receive interrupt source)

The request conditions for FIFO transmit or receive can be specified individually. The request

conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and

RFWM2 to RFWM0 bits in SIFCTR, respectively. Tables 21.9 and 21.10 summarize the

conditions specified by SIFCTR.

Table 21.9

Conditions to Issue Transmit Request

TFWM2 to TFWM0

Number of

Requested Stages

Transmit Request

Used Areas

000

Empty area is 16 stages

100

Empty area is 12 stages or more

101

Empty area is 8 stages or more

110

Empty area is 4 stages or more

Smallest

111

Empty area is 1 stage or more

Largest

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