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SH7721 Datasheet(PDF) 830 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 830 Page - Renesas Technology Corp

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Section 24
USB Host Controller (USBH)
Rev. 3.00 Jan. 18, 2008 Page 768 of 1458
REJ09B0033-0300
24.3.1
Hc Revision Register (USBHR)
Bit
Bit Name
Initial
Value
R/W
Description
31 to 8
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
6
5
4
3
2
1
0
Rev7
Rev6
Rev5
Rev4
Rev3
Rev2
Rev1
Rev0
0
0
0
1
0
0
0
0
R
R
R
R
R
R
R
R
Revision
These read only bits include the BCD expression of the
HCI specification version implemented for the host
controller. The value H'10 corresponds to version 1.0. All
HCI implementation complying with this specification have
the value of H'10.
24.3.2
Hc Control Register (USBHC)
The Hc Control register defines the operation mode for the host controller. The bits of this register
are amended only by the host controller driver (HCD) other than HCFS and RWC.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 11
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
10
RWE
0
R/W
Remote Wakeup Enable
This bit is set by HCD to enable/disable the remote
wakeup function at the same time as the detection of an
upstream resume signal.
This function is not supported. Be sure to write 0.



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