SH7721 datasheet(885/1524 Pages) RENESAS

885 / 1524 page

Section 25

USB Function Controller (USBF)

Rev. 3.00 Jan. 18, 2008 Page 823 of 1458

REJ09B0033-0300

25.3.22

EP4 Data Register (EPDR4)

EPDR4 is a 128-byte receive FIFO buffer for endpoint 4. EPDR4 has a dual-buffer configuration,

and has a capacity of twice the maximum packet size. The number of receive byte is displayed in

the EP4 receive data size register. The receive data is fixed when an SOF packet is received.

Accordingly, all receive data must be read until the next SOF packet is received. When the next

SOF packet is received, the FIFO side is automatically switched over, and the previous data will

not be possible to be read. This FIFO buffer can be initialized by means of EP4CLR in the FCLR1

Bit

Bit Name

Initial Value R/W Description

7 to 0 D7 to D0

Undefined

Data register for endpoint 4 transfer

25.3.23

EP5 Data Register (EPDR5)

EPDR5 is a 128-byte transmit FIFO buffer for endpoint 5. EPDR5 has a dual-buffer configuration,

and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO

buffer and an SOF packet is received, one packet of transmit data is fixed, and the dual-FIFO

buffer is switched over. This FIFO buffer can be initialized by means of EP5CLR and EP5CCLR

in the FCLR1 register. (EP5CLR initializes both FIFOs and EP5CCLR initializes one FIFO which

is connected to the CPU.)

Bit

Bit Name

Initial Value R/W Description

7 to 0 D7 to D0

Undefined

Data register for endpoint 5 transfer

25.3.24

EP0o Receive Data Size Register (EPSZ0o)

EPSZ0o is a receive data size resister for endpoint 0o. EPSZ0o indicates the number of bytes

received from the host.

Bit

Bit Name

Initial Value R/W

Description

7 to 0



All 0

Number of receive data for endpoint 0

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