SH7721 datasheet(887/1524 Pages) RENESAS

887 / 1524 page

Section 25

USB Function Controller (USBF)

Rev. 3.00 Jan. 18, 2008 Page 825 of 1458

REJ09B0033-0300

25.3.28

Data Status Register (DASTS)

DASTS indicates whether the IN FIFO data register contains valid data. DASTS is set to 1 when

data written to IN FIFO is enabled by writing PKTE in TRG to 1, and cleared when all data has

been transmitted to the host. In case of a dual-configuration FIFO for endpoint 2, this bit is cleared

to 0 when both sides are empty.

Bit

Bit Name

Initial Value R/W Description

7, 6



All 0

Reserved

These bits are always read as 0.

EP3 DE

EP3 Data Enable

EP2 DE

EP2 Data Enable

3 to 1



All 0

Reserved

These bits are already read as 0.

EP0iDE

EP0i data enable

25.3.29

FIFO Clear Register 0 (FCLR0)

FCLR is a one shot register to clear the FIFO buffers for endpoints 0 to 3. Writing 1 to a bit clears

the data in the corresponding FIFO buffer.

In case of reception FIFO, by writing data in the FIFO buffer, the data by which PKTE in TRG is

not written to 1 and the data enabled by writing 1 can be cleared. In case of OUT FIFO, the data of

which reception has not been completed can be cleared.

Both sides of the dual-configuration FIFO buffers (EP1 or EP3) can be cleared.

The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer

during transmission and reception.

Bit

Bit Name

Initial Value R/W

Description



Reserved

The write value should always be 0.

EP3 CLR



EP3 Clear

EP1 CLR



EP1 Clear

EP2 CLR



EP2 Clear

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