SH7721 datasheet(889/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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889 / 1524 page

Section 25

USB Function Controller (USBF)

Rev. 3.00 Jan. 18, 2008 Page 827 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value R/W Description

EP2 DMAE

R/W EP2DMA Enable

Enables DMA transfer for EP2.

EP1 DMAE

R/W EP1DMAE Enable

Enables DMA transfer for EP1.

25.3.32

Endpoint Stall Register 0 (EPSTL0)

EPSTL stalls each endpoint. The endpoint in which the stall bit is set to 1 returns a stall handshake

to the host from the next transfer when 1 is written to. The stall bit for endpoint 0 is cleared

automatically on reception of 8 byte command data for which decoding is performed by the

function and the EP0 STL bit is cleared. When the SETUPTS flag bit in the IFR0 register is set to

1, a write of the EP0 STL bit to 1 is ignored. For detailed operation, see section 25.8, Stall

Operations.

Bit

Bit Name

Initial Value R/W

Description

7 to 4



All 0

Reserved

This bit is always read as 0. The write value should

always be 0.

EP3 STL

R/W

EP3 Stall

Sets EP3 stall

EP2 STL

R/W

EP2 Stall

Sets EP2 stall

EP1 STL

R/W

EP1 Stall

Sets EP1 stall

EP0 STL

R/W

EP0 Stall

Sets EP0 stall

SH7721 Datasheet(PDF) 889 Page - Renesas Technology Corp

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