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SH7721 Datasheet(PDF) 891 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 891 Page - Renesas Technology Corp

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Section 25
USB Function Controller (USBF)
Rev. 3.00 Jan. 18, 2008 Page 829 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial Value R/W Description
2
1
0
ALTV2
ALTV1
ALTV0
0
0
0
R
R
R
Alternate Value
The alternate setting value is stored when the Set
interface command has been received.
ALTV is updated when the SETI bit in the interrupt
flag register is set to 1.
25.3.35
Time Stamp Register (TSRH/TSRL)
TSR is a register to store the current time stamp value. The time stamp is updated when the SOF
bit in IFR0 is set to 1. The value of the time stamp when the SOF mark function is enabled and the
SOF packet is broken remains as previous one.
Bit
Bit Name
Initial Value R/W
Description
15 to 11
All 0
R
Reserved.
This bit is always read as 0.
10
9
8
7
6
5
4
3
2
1
0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
Time Stamp Data
Note:
The time stamp register is used as a 16-bit register which consists of upper byte TSRH and
lower TSRL in USBF. TSRH can be read directly, but TSRL is read via an 8-bit temporary
register. Therefore, the registers should be accessed in the order, TSRH and TSRL, in byte
units. TSRL cannot be read singly.



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