SH7721 datasheet(921/1524 Pages) RENESAS

921 / 1524 page

Section 25

USB Function Controller (USBF)

Rev. 3.00 Jan. 18, 2008 Page 859 of 1458

REJ09B0033-0300

25.9

Usage Notes

25.9.1

Setup Data Reception

The following points should be noted on the EP0s data register (EPDR0s) in which reception of 8-

byte setup data is performed.

1. Since the setup command must be received in the USB, writing from the USB bus side is prior

to reading from the CPU side. While the CPU reads data after completion of reception and

reception of the next setup command is started, reading from the CPU side is forcibly invalid.

Therefore a value to be read after starting reception is undefined.

2. EPDR0s must be read in 8-byte units. If reading is suspended while it is in progress, data

received in the next setup cannot be read successfully.

25.9.2

FIFO Clear

When the USB cable is disconnected during communication, data which is receiving or

transmitting may remain in the FIFO. Therefore the FIFO must be cleared immediately after

connecting the USB cable again.

Note that the FIFO in which data is receiving from the host or transmitting to the host must not be

cleared.

25.9.3

Overreading/Overwriting of Data Register

The following points should be noted when the data register of the USBF is read from or written

to.

(1)

Receive Data Register

The receive data register must not read data which is more than valid receive data bytes. That is,

data which is more than bytes indicated in the receive data size register must not be read. In case

of the receive data register which has the dual FIFO buffer, the maximum number of data which

can be read in a single time is maximum packet size. Write 1 to TRG after data in the current valid

buffer is read. This writing switches the FIFO buffer. Then, the new number of bytes is reflected

in the receive data size and the next data can be read.

SH7721 Datasheet(PDF) 921 Page - Renesas Technology Corp