SH7721 datasheet(933/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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933 / 1524 page

Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 871 of 1458

REJ09B0033-0300

26.3.3

LCDC Data Format Register (LDDFR)

LDDFR sets the bit alignment for pixel data in one byte and selects the data type and number of

colors used for display so as to match the display driver software specifications.

Bit

Bit Name

Initial Value

R/W

Description

15 to 9



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

PABD

R/W

Byte Data Pixel Alignment

Sets the pixel data alignment type in one byte of

data. The contents of aligned data per pixel are the

same regardless of this bit's setting. For example,

data H'05 should be expressed as B'0101 which is

the normal style handled by a MOV instruction of the

this CPU, and should not be selected between

B'0101 and B'1010.

0: Big endian for byte data

1: Little endian for byte data



Reserved

This bit is always read as 0. The write value should

always be 0.

SH7721 Datasheet(PDF) 933 Page - Renesas Technology Corp