SH7721 datasheet(929/1524 Pages) RENESAS

929 / 1524 page

Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 867 of 1458

REJ09B0033-0300

26.3.1

LCDC Input Clock Register (LDICKR)

This LCDC can select the bus clock (B

φ), the peripheral clock (Pφ), or the external clock

(LCD_CLK) as its operation clock source. The selected clock source can be divided using an

internal divider into a clock of 1/1 to 1/32 and be used as the LCDC operating clock (DOTCLK).

The clock output from the LCDC is used to generate the synchronous clock output (LCD_CL2)

for the LCD panel from the operating clock selected in this register. For a TFT panel, LCD_CL2 =

DOTCLK, and for an STN or DSTN panel, LCD_CL2 = a clock with a frequency of

(DOTCLK/data bus width of output to LCD panel). The LDICKR must be set so that the clock

input to the LCDC is 66 MHz or less regardless of the LCD_CL2.

Bit

Bit Name

Initial Value

R/W

Description

15, 14



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

ICKSEL1

ICKSEL0

R/W

Input Clock Select

Set the clock source for DOTCLK.

00: Bus clock is selected (B

φ)

01: Peripheral clock is selected (P

φ)

10: External clock is selected (LCD_CLK)

11: Setting prohibited

11 to 9



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.



Reserved

This bit is always read as 1. The write value

should always be 1.

7, 6



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DCDR5

DCDR4

DCDR3

DCDR2

DCDR1

DCDR0

R/W

Clock Division Ratio

Set the input clock division ratio. For details on the

setting, refer to table 26.2.

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