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SH7721 Datasheet(PDF) 926 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 926 Page - Renesas Technology Corp |
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926 / 1524 page  Section 26 LCD Controller (LCDC) Rev. 3.00 Jan. 18, 2008 Page 864 of 1458 REJ09B0033-0300 Notes: 1. When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower bit lines should be connected to GND or to the lowest bit from which data is output. 2. For details, see section 26.4.1, LCD Module Sizes which can be Displayed in this LCDC. Figure 26.1 shows a block diagram of LCDC. Clock generator Pallet RAM LCDC Power control Register LCD_CLK Bus clock (B φ) Peripheral clock (P φ) Bus interface BSC External memory (VRAM) Line buffer 2.4 kbytes 4 bytes × 256 entries LCD_CL1 LCD_CL2 LCD_FLM LCD_DATA 15 to 0 LCD_DON LCD_VCPWC LCD_VEPWC LCD_M_DISP Peripheral bus DOTCLK Figure 26.1 LCDC Block Diagram |
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