SH7721 datasheet(930/1524 Pages) RENESAS

930 / 1524 page

Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 868 of 1458

REJ09B0033-0300

Table 26.2

I/O Clock Frequency and Clock Division Ratio

I/O Clock Frequency (MHz)

DCDR[5:0]

Clock Division

Ratio

50.000

60.000

66.000

000001

1/1

50.000

60.000

66.000

000010

1/2

25.000

30.000

33.000

000011

1/3

16.667

20.000

22.000

000100

1/4

12.500

15.000

16.500

000110

1/6

8.333

10.000

11.000

001000

1/8

6.250

7.500

8.250

001100

1/12

4.167

5.000

5.500

010000

1/16

3.125

3.750

4.125

011000

1/24

2.083

2.500

2.750

100000

1/32

1.563

1.875

2.063

Note:

Any setting other than above is handled as a clock division ratio of 1/1 (initial value).

26.3.2

LCDC Module Type Register (LDMTR)

LDMTR sets the control signals output from this LCDC and the polarity of the data signals,

according to the polarity of the signals for the LCD module connected to the LCDC.

Bit

Bit Name

Initial Value

R/W

Description

FLMPOL

R/W

FLM (Vertical Sync Signal) Polarity Select

Selects the polarity of the LCD_FLM (vertical sync

signal, first line marker) for the LCD module.

0: LCD_FLM pulse is high active

1: LCD_FLM pulse is low active

CL1POL

R/W

CL1 (Horizontal Sync Signal) Polarity Select

Selects the polarity of the LCD_CL1 (horizontal sync

signal) for the LCD module.

0: LCD_CL1 pulse is high active

1: LCD_CL1 pulse is low active

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