SH7721 datasheet(937/1524 Pages) RENESAS

937 / 1524 page

Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 875 of 1458

REJ09B0033-0300

26.3.5

LCDC Start Address Register for Upper Display Data Fetch (LDSARU)

LDSARU sets the start address from which data is fetched by the LCDC for display of the LCDC

panel. When a DSTN panel is used, this register specifies the fetch start address for the upper side

of the panel.

Bit

Bit Name

Initial Value

R/W

Description

31 to 28



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

27, 26



All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

25 to 4

SAU25 to

SAU4

All 0

R/W

Start Address for Upper Display Data Fetch

The start address for data fetch of the display data

must be set within the synchronous DRAM area of

area 3.

3 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

Notes: 1.

The minimum alignment unit of LDSARU is 512 bytes when the hardware rotation

function is not used. Write 0 to the lower nine bits. When using the hardware rotation

function, set the LDSARU value so that the upper-left address of the image is aligned

with the 512-byte boundary.

When the hardware rotation function is used (ROT = 1), set the upper-left address of

the image, which can be calculated from the display image size in this register. The

equation below shows how to calculate the LDSARU value when the image size is 240

× 340 and LDLAOR = 256. The LDSARU value is obtained not from the panel size but

from the memory size of the image to be displayed. Note that LDLAOR must be a

binary exponential at least as large as the horizontal width of the image. Calculate

backwards using the LDSARU value (LDSARU

− 256 (LDLAOR value) × (320 − 1)) to

ensure that the upper-left address of the image is aligned with the 512-byte boundary.

LDSARU = (upper-left address of image) + 256 (LDLAOR value)

× 319 (line)

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