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SH7721 Datasheet(PDF) 941 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 941 Page - Renesas Technology Corp |
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941 / 1524 page ![]() Section 26 LCD Controller (LCDC) Rev. 3.00 Jan. 18, 2008 Page 879 of 1458 REJ09B0033-0300 26.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) LDPR registers are for accessing palette data directly allocated (4 bytes x 256 addresses) to the memory space. To access the palette memory, access the corresponding register among this register group (LDPR00 to LDPRFF). Each palette register is a 32-bit register including three 8-bit areas for R, G, and B. For details on the color palette specifications, see section 26.4.3, Color Palette Specification. Bit Bit Name Initial Value R/W Description 31 to 24 R Reserved 23 to 0 PALDnn23 to PALDnn0 R/W Palette Data Bits 18 to 16, 9, 8, and 2 to 0 are reserved within each RGB palette and cannot be set. However, these bits can be extended according to the upper bits. Note: nn = H'00 to H'FF |
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