SH7721 datasheet(940/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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940 / 1524 page

Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 878 of 1458

REJ09B0033-0300

26.3.8

LCDC Palette Control Register (LDPALCR)

LDPALCR selects whether the CPU or LCDC accesses the palette memory. When the palette

memory is being used for display operation, display mode should be selected. When the palette

memory is being written to, color-palette setting mode should be selected.

Bit

Bit Name

Initial Value

R/W

Description

15 to 5



All 0

Reserved

These bits always read as 0. The write value should

always be 0.

PALS

Palette State

Indicates the access right state of the palette.

0: Display mode: LCDC uses the palette

1: Color-palette setting mode: The host (CPU) uses

the palette

3 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

PALEN

R/W

Palette Read/Write Enable

Requests the access right to the palette.

0: Request for transition to normal display mode

1: Request for transition to color palette setting mode

SH7721 Datasheet(PDF) 940 Page - Renesas Technology Corp