SH7721 datasheet(938/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 876 of 1458

REJ09B0033-0300

26.3.6

LCDC Start Address Register for Lower Display Data Fetch (LDSARL)

When a DSTN panel is used, LDSARL specifies the fetch start address for the lower side of the

panel.

Bit

Bit Name Initial Value

R/W

Description

31 to 28



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

27, 26



All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

25 to 4

SAL25 to

SAL4

All 0

R/W

Start Address for Lower Panel Display Data Fetch

The start address for data fetch of the display data

must be set within the synchronous DRAM area of

area 3.

STN and TFT: Cannot be used

DSTN: Start address for fetching display data

corresponding to the lower panel

3 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7721 Datasheet(PDF) 938 Page - Renesas Technology Corp

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