SH7721 datasheet(949/1524 Pages) RENESAS

949 / 1524 page

Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 887 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value

R/W

Description

MINTS

R/W

Memory Access Interrupt State

Indicates the memory access interrupt handling

state.

This bit indicates 1 when the LCDC memory access

interrupt is generated (set state). During the

memory access interrupt handling routine, this bit

should be cleared by writing 0.

0: LCDC did not generate a memory access

interrupt or has been informed that the generated

memory access interrupt has completed

1: LCDC has generated a memory access end

interrupt and not yet been informed that the

generated memory access interrupt has

completed

FINTS

R/W

Flame End Interrupt State

Indicates the flame end interrupt handling state.

This bit indicates 1 at the time when the LCDC

flame end interrupt is generated (set state). During

the flame end interrupt handling routine, this bit

should be cleared by writing 0.

0: LCDC did not generate a flame end interrupt or

has been informed that the generated flame end

interrupt has completed

1: LCDC has generated a flame end interrupt and

not yet been informed that the generated flame

end interrupt has completed

VSINTS

R/W

Vsync Start Interrupt State

Indicates the LCDC's Vsync start interrupt handling

state. This bit is set to 1 at the time a Vsync start

interrupt is generated. During the Vsync start

interrupt handling routine, this bit should be cleared

by writing 0 to it.

0: LCDC did not generate a Vsync start interrupt or

has been informed that the generated Vsync

start interrupt has completed

1: LCDC has generated a Vsync start interrupt and

has not yet been informed that the generated

Vsync start interrupt has completed

SH7721 Datasheet(PDF) 949 Page - Renesas Technology Corp

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