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SH7721 Datasheet(PDF) 950 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 950 Page - Renesas Technology Corp

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Section 26
LCD Controller (LCDC)
Rev. 3.00 Jan. 18, 2008 Page 888 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial Value
R/W
Description
8
VEINTS
0
R/W
Vsync End Interrupt State
Indicates the LCDC's Vsync end interrupt handling
state. This bit is set to 1 at the time a Vsync end
interrupt is generated. During the Vsync end
interrupt handling routine, this bit should be cleared
by writing 0.
0: LCDC did not generate a Vsync end interrupt or
has been informed that the generated Vsync end
interrupt has completed
1: LCDC has generated a Vsync end interrupt and
has not yet been informed that the generated
Vsync interrupt has completed
7 to 0
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.



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