SH7721 datasheet(954/1524 Pages) RENESAS

954 / 1524 page

Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 892 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value

R/W

Description

OFFF3

OFFF2

OFFF1

OFFF0

R/W

LCDC Power-Off Sequence Period

Set the period from stopping output of the display

data (LCD_DATA) and timing signals (LCD_FLM,

LCD_CL1, LCD_CL2, and LCD_M_DISP) to

LCD_VCPWC negation to in the power-off

sequence of the LCD module in frame units.

Specify to the value of (the period)-1.

This period is the (f) period in figures 26.4 to 26.7,

Power-Supply Control Sequence and States of the

LCD Module.

26.3.19

LCDC Control Register (LDCNTR)

LDCNTR specifies start and stop of display by the LCDC.

When 1s are written to the DON2 bit and the DON bit, the LCDC starts display. Turn on the LCD

module following the sequence set in the LDPMMR and LDCNTR. The sequence ends when the

LPS[1:0] value changes from B'00 to B'11. Do not make any action to the DON bit until the

sequence ends.

When 0 is written to the DON bit, the LCDC stops display. Turn off the LCD module following

the sequence set in the LDPMMR and LDCNTR. The sequence ends when the LPS[1:0] value

changes from B'11 to B'00. Do not make any action to the DON bit until the sequence ends.

Bit

Bit Name

Initial Value

R/W

Description

15 to 5



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DON2

R/W

Display On 2

Specifies the start of the LCDC display operation.

0: LCDC is being operated or stopped

1: LCDC starts operation

When this bit is read, always read as 0. Write 1 to

this bit only when starting display. If a value other

than 0 is written when starting display, the

operation is not guaranteed. When 1 is written to,

it resumes automatically to 0. Accordingly, this bit

does not need to be cleared by writing 0.

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