SH7721 datasheet(1018/1524 Pages) RENESAS

1018 / 1524 page

Section 28

D/A Converter (DAC)

Rev. 3.00 Jan. 18, 2008 Page 956 of 1458

REJ09B0033-0300

28.4

Operation

The D/A converter incorporates two D/A channels that can operate individually.

The D/A converter executes D/A conversion while analog output is enabled by the D/A control

immediately initiates the new data conversion. When the DAOE1 and DAOE0 bits in the DACR

An example of D/A conversion for channel 0 is shown below. The operation timing is shown in

figure 28.2.

1. Write conversion data to DADR0.

2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. The results are output after

the conversion has ended. The output value will be (DADR0 contents/256)

× AVcc.

The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is

cleared to 0.

3. When D/A data register 0 (DMDR0) is modified, the conversion starts again.

The results are output after the conversion has ended.

4. When the DAOE0 bit is cleared to 0, analog output is disabled (high-impedance state).

DADR0

Address bus

DADR0

write cycle

DADR0

write cycle

DACR

write cycle

DACR

write cycle

DAOE0

DA0

[Legend]

tDCONV: D/A conversion time

High impedance

state

Conversion result (1)

Conversion

result (2)

Conversion data (1)

Conversion data (2)

tDCONV

Figure 28.2

D/A Converter Operation Example

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