SH7721 datasheet(1099/1524 Pages) RENESAS

1099 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1037 of 1458

REJ09B0033-0300

31.3.5

Transfer Block Number Counter (TBNCR)

TBNCR sets the number of blocks to be transferred when multiblock transfer is specified by bits

TY5 and TY6 in CMDTYR. The contents of TBNCR is decremented for every 1-block transfer

completion. When the contents of TBNCR is 0, the command sequence is terminated, and an

interrupt is generated.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 0 TBNCR

All 0

R/W

Transfer Block Number Counter

[Clearing condition]

When the specified number of blocks are transferred and

0 is written to TBNCR.

31.3.6

Command Registers 0 to 5 (CMDR0 to CMDR5)

CMDR are six 8-bit registers. A command is written to CMDR as shown in table 31.3, and a

command is transmitted by setting the START bit in CMDSTRT to 1.

Table 31.3

CMDR Configuration

Contents

Operation

CMDR0

Start bit, Host bit, and

command index

Command index writing

Sets the Start bit to 0, and the Host bit to 1.

CMDR1 to CMDR4

Command argument

Command argument writing

CMDR5

CRC, End bit

Setting of CRC is unnecessary (automatic

calculation)

Setting of end bit is unnecessary (end bit is set to 1)

• CMDR0

Bit

Bit Name

Initial

Value

R/W

Description

Start

R/W

Start bit (This bit should be set to 0)

Host

R/W

Transmission bit (This bit should be set to 1)

5 to 0

INDEX

All 0

R/W

Command indexes

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