SH7721 datasheet(1098/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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1098 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1036 of 1458

REJ09B0033-0300

31.3.4

Transfer Byte Number Count Register (TBCR)

TBCR is an 8-bit readable/writable register that specifies the number of bytes to be transferred

(block size) for each single block transfer command. TBCR specifies the number of data block

bytes not including the start and end bytes and CRC.

The multiblock transfer command corresponds to the number of bytes of each data block. This

setting is ignored by the stream transfer command in MMC mode stream.

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

Transfer data block size

0000: 1 byte

0001: 2 bytes

0010: 4 bytes

0011: 8 bytes

0100: 16 bytes

0101: 32 bytes

0110: 64 bytes

0111: 128 bytes

1000: 256 bytes

1001: 512 bytes

1010: 1024 bytes

1011: 2048 bytes

1100 to 1111: Setting prohibited

SH7721 Datasheet(PDF) 1098 Page - Renesas Technology Corp