SH7721 datasheet(127/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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127 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 65 of 1458

REJ09B0033-0300

Type

Kinds of

Instruction

Op Code

Function

Number of

Instructions

Conditional branch, delayed conditional

branch (T = 0)

Conditional branch, delayed conditional

branch (T = 1)

BRA

Unconditional branch

BRAF

Unconditional branch

BSR

Branch to subroutine procedure

BSRF

Branch to subroutine procedure

JMP

Unconditional branch

JSR

Branch to subroutine procedure

Branch

instructions

RTS

Return from subroutine procedure

CLRMAC

MAC register clear

CLRS

S bit clear

System

control

instructions

CLRT

T bit clear

LDC

Load into control register

LDS

Load into system register

LDTLB

PTEH/PTEL load into TLB

NOP

No operation

PREF

Data prefetch to cache

RTE

Return from exception handling

SETS

S bit setting

SETT

T bit setting

SLEEP

Transition to power-down mode

STC

Store from control register

STS

Store from system register

TRAPA

Trap exception handling

Total:

188

The instruction code, operation, and number of execution states of the CPU instructions are shown

in the following tables, classified by instruction type, using the format shown below.

SH7721 Datasheet(PDF) 127 Page - Renesas Technology Corp

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