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SH7721 Datasheet(PDF) 301 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 301 Page - Renesas Technology Corp |
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301 / 1524 page ![]() Section 7 Exception Handling Rev. 3.00 Jan. 18, 2008 Page 239 of 1458 REJ09B0033-0300 • User break before instruction execution A user break before instruction execution is accepted at instruction [B], and an address of instruction [B] is saved in the SPC. This exception cannot be accepted at instruction [C] but the exception request is retained until an instruction [A] or [B] is executed at the next time. Then, the exception request is accepted before an instruction [A] or [B] is executed. In this case, an address of instruction [A] or [B] is saved in the SPC. • User break after instruction execution A user break after instruction execution cannot be accepted at instructions [B] and [C] but the exception request is retained until an instruction [A] or [B] is executed at the next time. Then, the exception request is accepted before an instruction [A] or [B] is executed. In this case, an address of instruction [A] or [B] is saved in the SPC. Table 7.4 Exception Acceptance in the Repeat Loop Exception Type Instruction [B] Instruction [C] Interrupt Not accepted Not accepted DMA address error Not accepted Not accepted User break before instruction execution Accepted Not accepted User break after instruction execution Not accepted Not accepted (4) CPU Address Error in Repeat Control Period If a CPU address error occurs in the repeat control period, the exception is accepted but an exception code (H'070) indicating the repeat loop period is specified in the EXPEVT. If a CPU address error occurs in instructions following a repeat detection instruction to repeat end instruction, an exception code for instruction access or data access is specified in the EXPEVT. The SPC is saved according to the description, SPC Saved by an Exception in Repeat Control Period in section 7.4.3, Exception in Repeat Control Period. After the CPU address error exception processing, the repeat control cannot be returned correctly. To execute a repeat loop correctly, care must be taken not to generate a CPU address error in the repeat control period. Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. In a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction. The restriction occurs when SR.RC[11:0] ≥ 1. |
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