SH7721 datasheet(305/1524 Pages) RENESAS

305 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 243 of 1458

REJ09B0033-0300

Section 8

Interrupt Controller (INTC)

The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt

requests to the CPU. The INTC registers set the priority of each interrupt, allowing the user to

process interrupt requests according to the user-set priority.

8.1

Features

• 16 levels of interrupt priority can be set

By setting the interrupt-priority registers, the priorities of on-chip peripheral modules, and IRQ

and PINT interrupts can be selected from 16 levels for individual request sources.

• NMI noise canceller function

An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt

exception service routine, the pin state can be checked, enabling it to be used as a noise

canceller.

• IRQ interrupts can be set

Detection of low level, high level, rising edge, or falling edge

• Interrupt request signal can be externally output (IRQOUT pin)

By notifying the external bus master that the external interrupt and on-chip peripheral module

interrupt requests have been generated, the bus mastership can be requested.

SH7721 Datasheet(PDF) 305 Page - Renesas Technology Corp