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SH7721 Datasheet(PDF) 306 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 306 Page - Renesas Technology Corp |
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306 / 1524 page  Section 8 Interrupt Controller (INTC) Rev. 3.00 Jan. 18, 2008 Page 244 of 1458 REJ09B0033-0300 Figure 8.1 shows a block diagram of the interrupt controller. Input/output control Priority identifier Com- parator Interrupt request SR CPU Bus interface INTC I3 I2 I1 I0 (Interrupt request) ICR IRR0 PINTER 6 4 16 IRQ5 to IRQ0 NMI PINT5 to PINT0 IRL3 to IRL0 IRLQOUT IPR [Legend] Interrupt control register Interrupt priority register Interrupt request register PINT interrupt enable register Refresh request in bus state controller ICR: IPR: IRR: PINTER: REF: DMAC SCIF SIOF TMU TPU WDT ADC USBF USBH RTC SIM LCDC PCC MMC I2C CMT AFEIF SSL SDHI REF Figure 8.1 Block Diagram of INTC |
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