SH7721 datasheet(310/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

310 / 1524 page

Section 8

Interrupt Controller (INTC)

Rev. 3.00 Jan. 18, 2008 Page 248 of 1458

REJ09B0033-0300

Table 8.2

Interrupt Sources and IPRA to IPRJ

Bits 15 to 12

Bits 11 to 8

Bits 7 to 4

Bits 3 to 0

IPRA

TMU0

TMU1

TMU2

RTC

IPRB

WDT

REF

SIM

Reserved*

IPRC

IRQ3

IRQ2

IRQ1

IRQ0

IPRD

Reserved*

TMU (TMU_SUNI) IRQ5

IRQ4

IPRE

DMAC (1)

Reserved*

LCDC

SSL

IPRF

ADC

DMAC (2)

USBF

CMT

IPRG

SCIF0

SCIF1

Reserved*

IPRH

PINTA

PINTB

TPU

IPRI

SIOF0

SIOF1

MMC

PCC

IPRJ

Reserved*

USBH

SDHI

AFEIF

Note:

Reserved. Always read as 0. The write value should always be 0. The SSL and SDHI-

related bits are effective only for the models that include them. Reserved bits apply if

they are not included.

As shown in table 8.2, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit

groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0)

are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is

requested); H'F means priority level 15 (the highest level).

SH7721 Datasheet(PDF) 310 Page - Renesas Technology Corp

SH7721 Datasheet(HTML) 310 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL